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TABLE 2.6 Effect of Conductor Widths on Number of Layers and Board Cost for a 6-in 8-in MLB, with Id = 450 in/in2, 65 to 68 Percent Yields Line-space 3 3 4 4 5 6 5 7 6 6 7 8 Total no. of layers 8 10 12 14 16 20 No. of signal layers 4 6 7 8 8 10 Board cost, % 55 64 77 87 90 100

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ensure the same connectivity (while their yields, interconnection density, and board area were kept constant). This reduction in the number of layers can significantly reduce the manufacturing costs of PWB boards.

(13.31)

Effect of Conductor Widths on Board Yields It is obvious that any successful increase of conductor density Id in PWBs would be effective only if the processes exist that permit manufacture with reasonable yields. Unfortunately, the yields of thin conductors in PWBs fall rapidly as their widths are reduced below 5 mils, as shown in Fig. 2.10. Therefore, the understanding of manufacturing yields is very important for analysis of the most cost-effective manufacturing process, because the process yields have a major effect on the cost of interconnection substrates.

Yield (%)

100 1000 Length of traces (in)

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getary reasons, the group decided to go it alone without a translator, since each party had a rudimentary knowledge of the three languages. Ultimately, the negotiations broke down into a shouting match as the representatives of each party translated what was said through their own lters and biases. The negotiation was tabled permanently, and all three organizations missed a good business opportunity. Ask yourself these questions: Do all members of your audience share the same language The same corporate language Do they share your language Do they need time to mentally translate your words Do they all know the acronyms and jargon that you ll be using Will you need an interpreter A negotiator

100 90 80 70 60 50 40 30 20 10 0 0

Yield loss (%)

400 600 Length of min. spacings (in)

Technology FR-4/glass, copper clad laminate Polyimide ( filled) copper-clad laminate Polyimide (unfilled) copper-clad laminate Proprietary dielectric (filled) copper-clad laminate Epoxy (filled) copper-clad laminate Ceramic thick-film Photopolymer (filled) Sol gel formation

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The use of more complex components with very high input/output (I/O) counts has pushed the board fabricator to reexamine techniques for creating smaller vias, and many new or redeveloped processes have appeared on the market. These processes include revised methods of creating holes, such as laser drilling, micro-punching, and mass etching; new methods for additively creating dielectric with via holes using photosensitive dielectric materials; and new methods for metallizing the vias such as conductive adhesives and solid post vias. All of these methods share some common traits. They all allow the designer to increase significantly routing density through the use of vias in surface-mount technology (SMT) pads, to reduce size and weight of product, and to improve the electrical performance of the system. These types of boards are generically called high-density interconnects (HDI). An HDI board typically will have, as an average, over 110 to 130 electrical connections per square inch (20 connections per sq. cm) on both sides of the board.

Printed wiring boards (PWBs) with microvia hole structures are called different names, such as HDI, SBU (sequential build-up), and BUM (build-up multilayer). However, HDI covers a broader range of high-density wiring boards such as extremely high-layer-count multilayer boards (MLBs) without microvia holes. MLBs with microvia holes are not necessarily built sequentially, nor do they necessarily have build-up structures.These definitions are not appropriate for the discussions in this chapter, and therefore we shall address MLBs with microvia holes simply as microvia hole boards (all microvia hole boards are essentially multilayer boards). Some trade and academic organizations define the microvia hole to be a hole of a certain diameter or less. For example, IPC defines a microvia hole as a hole with a diameter equal to or less than 150 m. However, when a surface blind via (SBV) hole is formed between layer 1 (L1)

and layer 3 (L3), the diameter of such a hole is typically 250 m in order to facilitate reliable plating, but the hole is still considered a microvia hole Since all microvia holes are essentially SBVs and are normally small in diameter in order to increase circuit density, it seems more appropriate to define the microvia hole as an SBV without limiting its diameter As long as a hole has SBV structure, it is defined as a microvia hole throughout this chapter The first microvia PCB in general production: (a) Hewlett Packard s FINSTRATE was put into production in 1984 It was a copper-core, build-up technology that had direct wirebonded integrated circuits (ICs) After laminating layers of plasma-metalized polytetrafluoroethylene (PTFE) to the copper core, vias were mechanically drilled through the copper core and then insulated with PTFE Additional through holes were then drilled along with 5 mil blind vias.

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